



Algorithm to FPGA: Automated HDL Generation with C/C++ - Round 1
EGP 2500.00
By Mervat Mahmoud
- mervat-m@eri.sci.eg
Starts on 26-Jan-2025
Category: Digital Electronics
Level: Intermediate
Description
- High-Level Synthesis (HLS): Benefits and challenges. - C++ Fundamentals - Writing synthesizable C code for hardware design - Data Flow Graphs (DFG), Pipelining, and Unrolling - Project
Prerequisites
Knowledge of HDL Language (Verilog or VHDL).Knowledge of C language.